Flow Audit and Development

fastest-to-silicon

Flow Audit and Development


ASIC design has a very large scope starting from RTL development to tapeout and beyond. It is a big challenge to maintain the quality of the product at every step of the process. The quality of the flow dictates the quality of the product after the step. Due to varying chip size and technology, we always need to improve the flows to ensure its quality.

PrimeSilicon provides a large array of solutions related to the flows.

The primary two aspects here are:

  • Development of flow
  • Auditing the existing flow

We have flows including but not limited to below examples:

  • PnR tools from Synopsys, Cadence and Avatar
  • Signoff tools from Synopsys and Cadence
  • DFT Insertion and Validation

Here is an example concept of our PNR flow:

  • Design import and linking
  • Floorplan and Power-Plan
  • Placement
  • Clock Tree Synthesis and Optimization
  • Routing and manufacturability flow

Here are a few key scopes of our PNR Audit Flow:

  • IP Integration Quality Check (QC)
  • Special Macro Placement QC
  • Netlist connectivity analysis and related audits
  • Clock tree and related metrics QC
  • DFT QC
  • Constraints QC