High-Speed Fiber-Optic PHY Tapeouts

High-speed optical chips live or die on signal integrity. We co-designed floorplans with the analog team so SerDes, PLL and data-converter blocks sat in quiet, well-shielded regions, and used custom layout wherever automated routing could not meet the channel budget.

Mixed-signal integration was verified end to end — analog/digital boundary checks, multi-domain power intent and full-chip physical verification — before each of the tapeouts in the program.

The program delivered multiple tapeouts of fiber-optic networking chips — the class of high-bandwidth interconnect silicon that now links AI training clusters across the data center.

Successful Tapeouts

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Years of ASIC Design Excellence

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High-Speed Fiber-Optic PHY Tapeouts

Brief and project description

Process

Key Outcomes

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